A problem which is associated with the development of programmable logic devices is how to test and verify the internal logic of such devices. One technique which has been commonly used for this purpose is software simulation. Software simulation, however, has several disadvantages. In particular, software simulation tends to be computationally intensive, and therefore, very slow. In addition, a substantial amount of time and expense may be required to develop and then analyze an appropriate software simulation model. In addition, because the software stimulus is prepared by humans, software simulation techniques tend to be susceptible to errors.
Hardware based approaches also have disadvantages. For example, many hardware based approaches have been very complex and difficult to use. Certain hardware simulation systems have proven susceptible to latent flaws in the electronics for stimulating the target device and analyzing its outputs; such flaws have been known to cause a target device to be inadvertently stimulated while analyzing the outputs, resulting in erroneous simulation results. Other testing approaches, such as JTAG, have included designing extra circuitry into a logic device specifically for testing purposes. In the design of integrated circuits, however, in which the amount of available chip area and the number of available pins may be limited, it is not desirable to consume chip area and pins for testing purposes. In addition, JTAG and other similar techniques do not allow the real-time trace out of multiple internal nodes of a logic device and do not provide continuous-in-time information about the state of a node. Rather, information about a node can only be traced out based on the rate of the clock used to latch the internal node to the JTAG register.
Hence, it is desirable to have an efficient, reliable, and inexpensive technique by which a programmable logic device can be tested in a short period of time and in a manner that is not disruptive to the target device. It is further desirable to have such a technique which does not require extra circuitry or extra pins on the device to be tested. It is further desirable that such a technique allow real-time, continuous trace out of multiple internal nodes of a programmable logic device and allow quick tests and comparisons of different logic designs, which may be based on different design assumptions.